1) Field of the Invention
This invention relates generally to a process for etching silicon nitride (SiN) spacers on sidewalls of gate electrodes of semiconductor devices.
2) Description of the Prior Art
Spacers are widely used in manufacturing as protective structure against subsequent processing steps. In particular, nitride spacers formed beside gate electrodes are used as a mask to protect underlying source/drain areas during doping or implanting steps.
As physical geometry of semiconductor devices shrinks, the gate electrode spacer becomes smaller and smaller. The spacer width is limited by nitride thickness that can be deposited conformably over the dense gate electrodes lines. So the nitride spacers etching process is preferred to have a high ratio of spacer width to nitride layer thickness as deposited (we call this ratio the width to thickness ratio). At the same time high selectivity or nitride to oxide is required to prevent damage on silicon substrate. The conventional F based chemistry gives relatively high selectivity, but low width thickness ratio. The existing Cl based chemistry gives relatively high width to thickness ratio but low selectivity.
The patent of Babie et al. (U.S. Pat. No. 5,431,772, July 1995) described a two-step method of etching silicon nitride film, and was mainly concerned with the problem of possible contamination of the surface of the silicon nitride film by oxygen-containing substances such as silicon dioxide or silicon oxynitride. That invention comprises a first step of removing the surface oxide or oxynitride from the silicon nitride layer in a reactive plasma of fluorine-containing gases consisting essentially of SF.sub.6, CF.sub.4, C.sub.2 F.sub.6 and NF.sub.3. In the second step, the main etch: step, the silicon nitride layer is etched with a high selectivity with respect to the etching of the silicon dioxide underlayer, using a reactive plasma gas mixture of HBr, or HBr and SiF4, and an oxidant selected from the group consisting of O.sub.2, CO.sub.2, or N.sub.2 O and a diluent gas such as He, N2, or Ar. The optimum process conditions are described to be as follows: HBr flow 20.00 sccm, O.sub.2 flow 0.45 sccm, He flow 1.05 sccm, pressure 100 mTorr, power density 1.65 W/cm.sup.2, magnetic field 45 gauss, giving an etch rate of 600 ANG./min. They have mentioned a Si.sub.3 N.sub.4 /SiO.sub.2 etch selectivity of 12.6:1.
Other prior art inventions have also described silicon nitride etch processes with high selectivities with respect to silicon dioxide underlayer.
In the fabrication of all kinds of integrated circuit devices, a high Si3 N4/SiO2 etch selectivity is important for accurately controlling the etch end point and preventing damage to the silicon substrate by over etching the oxide. The enhancement of the Si.sub.3 N.sub.4 /SiO2 etch selectivity is the aim of the prior art inventions mentioned above. However, these prior art inventions have not addressed issues that become very important in the fabrication of submicron devices, and particularly devices that are 0.5 .mu.m or smaller. A very important issue is the requirement of the ability of the etch process to accurately conform to the critical dimension of these small devices. A very high degree of etch anisotropy is desirable to produce highly vertical sidewalls of the silicon nitride spacer, thereby conforming to the critical dimension from the top to the bottom of the silicon nitride spacer. A low etch anisotropy will produce undesirable sloping sidewalls of the silicon nitride layer, causing deviation from the required critical dimension and a low width to thickness ratio (less than 0.9).
Beside the silicon nitride etch processes described by the aforementioned prior art inventions, traditional nitride etch process currently in use is a two-step process comprising a main step using SF6 and He in the gaseous plasma to get near the end point, and a second step of high Si.sub.3 N.sub.4 /SiO.sub.2 etch selectivity using SF.sub.6 and O.sub.2 in the gaseous plasma so as to prevent the occurrence of non-uniform patches of unremoved silicon nitride without unduly over-etching the pad oxide underneath the silicon nitride. Thus, the second etch step is an over-etch step for silicon nitride, but is one that will not over etch the pad oxide.
The importance of overcoming the various deficiencies noted above is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The closest and apparently more relevant technical developments in the patent literature can be gleaned by considering the following patents.
U.S. Pat. No. 5,431,772(Babie et al.) shows a SiN etch using O.sub.2 /HBr and He.
U.S. Pat. No. 4,818,715(Chao) shows a poly gate stack etch with a SiN layer 42. See Col. 6.
U.S. Pat. No. 5,854,136(Huang et al.) shows a three step etch process with HBr, SF.sub.6 and He.
U.S. Pat. No. 5,338,395(Keller et al.) shows another SiN etch process.